When emulating a user design for verifying low-power performance, memories in the user design are loaded with a pseudo-random pattern. Those memories loaded with the pseudo-random pattern are used either to test permanent data loss when the memory is power cycled, or to test memory read/write functions in a low-power state. The power domain in the user design that drives the memory read/write functions changes the power state not only during the initialization but also while the user design is running.
When the user design is emulated with a dynamic target (e.g., external logic analyzer) in a logic analyzer (LA) mode, test clocks cannot be paused once they start, and the emulation must run through until it reaches a breakpoint. Therefore, memories in a user design need to be randomized within the emulator while the user design is running.
When emulating without a dynamic target, for example in synthesizable test bench (STB) mode, the emulator detects changes in the power state and pauses the emulation by stopping the emulation clock. During the pause, the software running in the host workstation downloads a random pattern into the memory, and restarts the emulation clock to resume the emulation.
The memory read functionality of the user design in a low-power state is tested by reading and storing the original memory content, loading a random pattern to the memory, and writing the stored memory contents back to the memory when full power is restored. The memory content written in the full power state is compared with those read in the lower power state to verify that the memory read failed during the low-power state.
However, the emulation with a dynamic target such as a logic analyzer cannot be run in a STB mode because the emulation run typically cannot be paused once started. Other solutions have been proposed to overcome this problem. However, there is currently no known solution for emulating a user design in a logic analyzer (LA) mode without containing a state machine for randomizing memory during the emulation.
Memory randomization in a STB mode is functional but slow because the emulation repeatedly stops and resumes. The pause/resume functions are performed by a host workstation require interruption each time the emulation stops and restarts. Many STB mode approaches also require an emulation clock per each memory location. The memory in a user design that needs to be randomized and written during emulation may have billions of locations. In addition, the emulation clock cycles need to be visible to the user design during the emulation for memory randomization. In a typical circuit design, the emulation clocks are not visible and some user designs can only provide limited visibility of their emulation clocks for memory randomization and testing.
The present invention overcomes the above-identified shortcomings of prior art memory randomization techniques and provides benefits and solutions for efficient randomization and testing of a memory in a user design during an emulation.